1. Field of the Invention
The present invention relates to multichip modules (MCM) and a manufacturing method therefor, and more particularly to multichip modules and a manufacturing method in which a recess is provided in a substrate during manufacturing of the substrate of a ball grid array integrated circuit for receiving an integrated circuit or memory stack.
2. Description of the Related Art
In order to reduce the volume of an electric device, integrated circuits are packaged in stacks to form a multichip module to reduce the surface area of the substrate occupied by the electric device.
U.S. Pat. No. 5,323,060 to Fogal et al. issued on Jun. 21, 1994 discloses a multichip module having a stacked chip arrangement. In this patent, as shown in FIG. 1 of the drawings that corresponds to FIG. 1 of U.S. Pat. No. 5,323,060, the multichip includes a substrate 100, a first multichip stack 110, and a second multichip stack 120. The first multichip stack 110 includes a first chip 112 mounted to a bonding area 111 of the substrate 100. An adhesive layer 113 is applied to upper face of the first chip 112. A second chip 114 is then mounted on top of the adhesive layer 113, thereby forming a multichip stack with two chips. A number of bonding wires 115 interconnect bonding pads of the chips 112 and 114 and bonding pads of the substrate 100. The adhesive layer 113 must have a thickness of "A" to allow connection between the bonding wires 115 and the bonding pads of the chips 112 and 114. The second multichip stack 120 includes a first chip 122 mounted to a bonding area 121 of the substrate 100. A first adhesive layer 123 is applied to upper face of the first chip 121. A second chip 124 is mounted on top of the first adhesive layer 123, and a second adhesive layer 125 is then applied to upper face of the second chip 124. Next, a third chip 126 is mounted on top of the second adhesive layer 125, and a third adhesive layer 127 is applied to upper face of the third chip 126 for mounting a further chip, thereby forming a multichip stack with many chips. A number of bonding wires 128 interconnect bonding pads of the chips 122, 124, and 126 and bonding pads of the substrate 100. The adhesive layers 123, 125, and 127 must have a thickness of "A" to allow connection between the bonding wires 128 and the bonding pads of the chips 122, 124, and 126. Nevertheless, the adhesive layers 113, 123, 125, and 127 must have a thickness of "A" to prevent the chips 114, 124, or 126 from making contact with the underlying bonding wires 115 or 128. Yet the increase in the thickness of the adhesive layers 113, 123, 125, and 127 results an obstacle to heat transfer from the chips 114, 124, and 126 to the underlying chips. The heat dissipating effect is accordingly poor.
U.S. Pat. No. 5,804,004 to Tuckerman et al. issued on Sep. 8, 1998 discloses stacked devices for multichip modules. In this patent, as shown in FIGS. 2 and 3 of the drawings that correspond to FIGS. 4A and 4B of U.S. Pat. No. 5,804,004, the multichip includes a substrate 200, and a first chip 211 is mounted to upper face of the substrate 200 by an adhesive layer ai 210. Bonding pads 215 of the first chip 211 are connected to bonding pads 201 of the substrate 200 by bonding wires 214. A second chip 212 is mounted to upper face of the first chip 211 by an adhesive layer 210. Bonding pads 215 of the second chip 212 are connected to bonding pads 202 of the substrate 200 by bonding wires 214. Bonding wires 214 are prevented from making contact with the adjacent upper chip 212 by beveling the edge of the upper second chip 212. A third chip 213 is mounted to upper face of the second chip 212 by an adhesive layer 210. Bonding pads 215 of the third chip 213 are connected to bonding pads 203 of the substrate 200 by bonding wires 214. Bonding wires 214 are prevented from making contact with the adjacent upper chip 213 by beveling the edge of the upper third chip 213. Nevertheless, beveling of the edge of the chip 212, 213 results in difficulty in manufacturing.